Silicon-On-Insulator (SOI) substrates have been drawing attention in recent years, in order to achieve higher performance for semiconductor devices. Silicon-On-Quartz (SOQ) substrates and Silicon-On-Sapphire (SOS) substrates, etc., which have a support substrate (handle wafer) devoid of silicon, each has been used in fields such as TFT-LCDs and high-frequency (RF) devices.
While there are some methods for manufacturing the bonded wafer, the SmartCut™ method can be typically used. In this method, hydrogen ions are implanted into a single-crystal silicon substrate with an oxide film formed (a donor wafer, also referred to as a first substrate in the specification), the single-crystal silicon substrate is attached to a support substrate (a handle wafer, also referred to as a second substrate in the specification), and then heated to around 500° C., and splits the silicon substrate along the hydrogen ion-implanted region so as to transfer the single-crystal silicon thin film to the handle wafer. In this case, the formation of minute hydrogen cavities referred to as microcavities at the hydrogen implanted region allows the split at the interface. After that, in the SmartCut™ method, in order to increase the bonding strength between the single-crystal silicon thin film and the handle wafer, a heat treatment at a high temperature of 1000° C. or more is carried out, followed by a final surface treatment (CMP, a heat treatment, etc.) (See e.g. Patent Documents 1 and 2 and Non-Patent Document 1).
On the other hand, in the SiGen method, prior to attaching a silicon substrate with a surface to be attached and with the surface subjected to implantation of hydrogen ions or the like to a silicon substrate or a substrate of the other material, one or both of the surfaces of these substrates to be attached are subjected to a plasma treatment, the both substrates are attached to each other with the surface(s) activated, and subjected to a heat treatment at a low temperature such as, for example, 350° C. to increase bonding strength, and mechanical split is then carried out at ordinary temperature to obtain an bonded SOI wafer (see e.g. Patent Documents 3 to 5).
The difference between these two methods mainly consists in the process for splitting a silicon thin film, and is that the SmartCut™ method requires a treatment at a high temperature for splitting of a silicon thin film, whereas the SiGen method is capable of splitting at ordinary temperature.
In particular, when a semiconductor substrate such as a silicon substrate is attached to another substrate to manufacture a bonded wafer, the obtained wafer tends to have breaks or cracks due to the differences in the thermal expansion coefficient and the allowable temperature limit between the different materials. Thus, it is desirable to carry out the steps up to the split treatment at a temperature as low as possible. Therefore, the SiGen method, which is capable of splitting at a low temperature, may be preferable as a method for manufacturing a bonded wafer by the attachment of two substrates made of different materials.
In the meanwhile, in the method for manufacturing a bonded wafer comprising the lamination step as described above, the obtained wafer often has defects devoid of semiconductor layers, which are also referred to as voids, due to contaminant or gasses slipping into the attaching interface. These defects such as voids will cause problems in the manufacture of devices, and are thus desired to be reduced as much as possible. The voids are caused when the surfaces of the attaching layers fail to be closely bonded to each other due to contaminant, etc., so that the weakly attached or unattached portion of the semiconductor layer fails to be printed on the support layer in the splitting step. In order to prevent the occurrence of such voids, the cleanness of the substrate or the environment prior to the lamination is important. Therefore, the substrates are cleaned right before the attachment and the cleanness of the atmosphere for the attachment is kept at a high level.
However, the methods for manufacturing a bonded wafer tends to have voids, in particular, at the lamination terminal point even if the cleanness of the substrate prior to the attachment and the cleanness of the environment for the attachment are both kept at high levels. In addition, in order to prevent voids at the lamination terminal point, further high level cleanness is required, but enormous costs and efforts are required to that end.    Patent Document 1: Japanese Patent No. 3048201    Patent Document 2: Japanese Patent Application Laid-Open No. 11-145438    Patent Document 3: U.S. Pat. No. 6,263,941    Patent Document 4: U.S. Pat. No. 6,513,564    Patent Document 5: U.S. Pat. No. 6,582,999    Non-Patent Document 1: Auberton-Herve et al., “SMART CUT TECHNOLOGY: INDUSTRIAL STATUS of SOI WAFER PRODUCTION and NEW MATERIAL DEVELOPMENTS” (Electrochemical Society Proceedings Volume 99-3 (1999) p. 93-106)